The present invention relates to the fabrication of semiconductor integrated circuits (IC's). More particularly, the present invention relates to methods and apparatuses for etching through an IC's layer stack to produce a top rounded isolation feature.
During the manufacture of a semiconductor-based product, for example, a flat panel display or an integrated circuit, multiple deposition and/or etching steps may be employed. By way of example, one method of etching is plasma etching. In plasma etching, a plasma is formed from the ionization and dissociation of process gases. The positively charged ions are accelerated towards the substrate where they, in combination with neutral species, drive the etching reactions. In this manner, etched features such as vias, contacts, or trenches may be formed in the layers of the substrate.
Recently, shallow trench isolation (STI) has grown in popularity as a preferred method for forming a trench that can, among other applications, electrically isolate individual transistors in an integrated circuit. Electrical isolation is needed to prevent current leakage between two adjacent devices (e.g., transistors). Broadly speaking, conventional methods of producing a shallow trench isolation feature include: forming a hard mask over the targeted trench layer, patterning a soft mask over the hard mask, etching the hard mask through the soft mask to form a patterned hard mask, and thereafter etching the targeted trench layer to form the shallow trench feature. Subsequently, the soft mask is removed (e.g., stripped) and the shallow trench isolation feature is back-filled with a dielectric material.
FIGS. 1A-1C are cross section views of the conventional process steps that maybe used to form shallow trench isolation features. Referring initially to FIG. 1A, there is shown a typical layer stack 10 that is part of a substrate or semiconductor wafer. (not drawn to scale for ease of illustration). A silicon layer 12 is located at the bottom of layer stack 10. A pad oxide layer 14 is formed above silicon layer 12 and a nitride layer 16 is formed above pad oxide layer 14. In most situations, the pad oxide layer is used as the interlayer that is disposed between the nitride layer and the silicon layer. Furthermore, in order to create a patterned hard mask with pad oxide layer 14 and nitride layer 16, a photoresist layer 18 is deposited and patterned using a conventional photolithography step over nitride layer 16. After patterning, soft mask openings 20 (narrow) and 22 (wide) are created in photoresist layer 18 to facilitate subsequent etching. The above-described layers and features, as well as the processes involved in their creation, are well known to those skilled in the art.
Following the formation of layer stack 10, nitride layer 16 and pad oxide 14 are subsequently etched to create a hard mask, which includes a narrow hard mask opening 24 and a wide hard mask opening 26, as seen in FIG 1B. The hard mask openings are used to pattern the trench during etching of the silicon layer. For the most part, etching stops after reaching silicon layer 12, however, a small portion 28 on the surface of silicon layer 12 is typically etched away during the etching of pad oxide layer 14. Moreover, a gas chemistry that includes CF4 is generally used to facilitate etching through the nitride and pad oxide layers. Typically, the CF4 chemistry etches the side walls of nitride layer 16, pad oxide layer 14 and small portion 28 of silicon layer 12 anisotropically (i.e., substantially straight down).
Once hard mask openings are created through nitride layer 16 and pad oxide layer 14, silicon layer 12 is etched therethrough to form shallow trench isolation features, for example, a narrow feature 30 and a wide feature 32, as shown in FIG. 1C.
Typically, a gas chemistry that includes Cl.sub.2 and/or HBr is used to facilitate etching through the silicon layer. Subsequent to the steps shown in FIGS. 1B&1C, the mask layers are removed, leaving a trench disposed in the silicon layer. Typically, thereafter, the trenches are filled with a dielectric material such as an oxide (e.g., TEOS) to complete the formation of the shallow trench isolation.
Typically, the shallow trench isolation features, etched in silicon, produce a harp corner 34 in the vicinity of the interface of pad oxide layer 14 and silicon layer 12. If there is a sharp corner at the top of the feature when a dielectric material is deposited into the feature, the dielectric material may wrap around the corner creating a layer with varying thickness. Typically, the dielectric material (e.g., oxide) is the thinnest at the sharp corner. In some cases, the thin region at the sharp corner may cause a gate leakage problem. Adversely, gate leakage tends to cause malfunctions in the semiconductor device (e.g., threshold voltage problems).
Additionally, in shallow trench isolation, the etch results tend to differ based on the geometry of the feature (e.g., narrow spaces and wide spaces). Typically, wide trenches have an increased etch rate over narrow trench etch rates. Correspondingly, differing etch rates tend to create a depth difference between the features. Referring to FIG. 1C, a depth difference 36 is shown between narrow feature 30 and wide feature 32. Trenches of varying depths may have adverse impacts on the functioning of the device. By way of example, if a depth non-uniformity exists between two features during subsequent deposition steps (e.g., filling the feature with dielectric), a non-level top surface may be encountered (i.e., more dielectric in one area and less dielectric in another area). Significant yield problems may be encountered when the top surface of the substrate is not flat or level. For this reason, it is desirable to create trenches that have substantially similar depths. Preferably, for a smooth functioning device, the depth difference is between 2 to 5% or even lower. However, the semiconductor industry often sees more than a 12.5% difference between the depths of the narrow features and the wide features.
In view of the foregoing, there are desired improved techniques for etching features having rounded corners, substantially equal depths and similar profiles. Also, desired are etch techniques that may be implemented "in situ," in other words, in one plasma processing chamber. Historically, trench features have been etched with a sequential process flow, where the mask layers are etched in one chamber and the silicon trench is etched in another chamber. A significant improvement in productivity can be achieved if the mask and trench etch is performed in situ (in the same chamber).